1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a method for forming wells of a semiconductor device.
2. Discussion of the Related Art
In order to improve performance of a semiconductor device, impurity ions of an opposite conductive type to that of a semiconductor substrate are first implanted into the semiconductor substrate to form wells. Then, unit devices are formed on the semiconductor substrate.
Different kinds of wells are formed by using different methods. For diffused wells, e.g., a single well, twin wells, triple wells, ions are entirely or partially implanted into the semiconductor substrate and then diffused prior to performing a device-isolating process. For retrograde wells, ions are implanted by adjusting the ion-implantation energy to form wells of different types after performing a device-isolating process. Also, some retrograde wells have a buried implanted layer for lateral isolation (BILLI) structure.
A diffusion process can be performed to a desired depth from surface of the substrate to form a single well and twin wells. In this case, diffusion proceeds both vertically and horizontally. As a result, it is difficult to form a desired profile and the process tolerance becomes smaller. For this reason, triple wells are preferred to twin and single wells. However, the process of forming triple wells is very complicated and thus leads to low productivity. Therefore, research and development efforts are currently directed to simplifying the fabrication process for triple wells.
A conventional method for forming wells of a semiconductor device will be discussed with reference to FIGS. 1A to 1G. As shown in FIG. 1A, a first oxide layer 2 and a first nitride layer 3 are successively formed on a semiconductor substrate by a chemical vapor deposition (CVD) process.
Referring to FIG. 1B, a photoresist film 4 is coated on the first nitride layer 3 and then patterned by an exposure and development process. With the photoresist pattern 4 serving as a mask, the first nitride layer 3 is partially removed. Next, phosphorus ions are implanted into the semiconductor substrate 1 with a high energy of 500 KeV to form an n-shield region 5 in a predetermined depth. In this case, the photoresist film 4 has a thickness of 4 .mu.m to prevent the high energy phosphorus ions from implanting to the semiconductor substrate 1 under the photoresist pattern 4.
Referring to FIG. 1C, the remaining photoresist film 4 is removed. Then, a thermal oxidation process is performed over the semiconductor substrate 1 to form a second oxide layer 6, which functions as an align key to discern a cell region from a periphery region.
Referring to FIG. 1D, the first nitride layer 3, the first oxide layer 2, and the second oxide layer 6 are all removed. A third oxide layer 7 and a second nitride layer 8 are deposited on the semiconductor substrate 1 with a CVD process. As shown in FIG. 1D, a step coverage is generated on the portion of the semiconductor substrate 1 where the second oxide layer 6 is removed.
Referring to FIG. 1E, another photoresist film 9 is coated on the semiconductor substrate 1 and then selectively patterned by an exposure and development process to be removed over a periphery portion of the n-shield region 5 and over a portion separated by a predetermined distance from the periphery portion of the n-shield region 5. With the photoresist pattern 9 serving as a mask, the second nitride layer 8 and the third oxide layer 7 are partially removed. Thereafter, phosphorus ions are implanted into the exposed semiconductor substrate 1 with a low implantation energy to form first and second n-wells 10a and 10b. The first and second n-wells 10a and 10b are formed at a shallower depth than the n-shield region 5. Here, the first n-well 10a is placed above the n-shield region 5 and the second n-well 10b is formed a distance away from the n-shield region 5.
Referring to FIG. 1F, with the photoresist pattern 9 serving as a mask, a fourth oxide layer 11 is formed on the exposed semiconductor substrate 1. After the second nitride layer 8 and the remaining photoresist film 9 are removed, either p-type B ions or BF.sub.2 ions are implanted to form first and second p-wells 12a and 12b by an self-alignment process. At this time, the first and second p-wells 12a and 12b are formed at the same depth as the first and second n-wells 10a and 10b. The first p-well 12a is placed above the n-shield region 5 and next to the first n-well 10a. The second p-well 12b is placed between the first and second n-wells 10a and 10b.
Referring to FIG. 1G, the fourth oxide layer 11 is removed. The first and second n-wells 10a and 10b and the first and second p-wells 12a and 12b are diffused by a driven-in process. At this time, the first p-well 12a is diffused down to the boundary of the n-shield region 5 and the first n-well 10a is diffused to the n-shield region 5. And the second n-well 10b is diffused to the same depth as the first n-well 10a. The second p-well 12b is diffused between the first n-well 10a and the second n-well 10b. Therefore, the first p-well 12a in the cell region is isolated from the second p-well 12b in the periphery region.
The conventional method for forming wells of a semiconductor device has the following problems. First, since several diffusion processes and CVD processes are required, the overall process is complicated and thus leads to inferior productivity. Further, when a cell region and a periphery region are isolated from each other through CVD processes, a step coverage is created between a first n-well in the cell region and a second p-well in the periphery region.